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I am writing a 64-bit adder module, and my inputs are a,b,cin and my outputs are sum and carry. I want to use a continuous assignment, and so I wrote assign sum = (a + b); before my end module. In order to also assign this value to my carry, would assign sum,carry = (a + b); be the correct syntax? I also saw online that it should include curly brackets assign {sum, carry} = (a + b); but it was not explicitly stated.

noface
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  • Does this answer your question? [Curly braces in verilog](https://stackoverflow.com/questions/38894112/curly-braces-in-verilog) – dave_59 Nov 13 '20 at 19:32

1 Answers1

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It should include curly brackets.

{  ,  ,  }

This is the concatenation operator in Verilog. So,

assign {carry,sum} = (a + b);

Is what you want. (Note that in Verilog the LSB is always on the right hand side, so the carry needs to be on the left.)

Matthew Taylor
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