Conditional OR in makefile

Question

I'd like to enable a verbose compilation in my makefile, but I can't figure out how to make a conditional OR.

Let me explain: I want to be able to specify a verbose compilation either by setting V=1 or VERBOSE=1. I want to keep VERBOSE=1 available because we have some scripts that make use of it (and use other makefiles only aware of VERBOSE)

So the result must be that these two commands are the same:

make all VERBOSE=1 # pain to write
make all V=1

Now, my makefile looks like this today:

ifdef VERBOSE
[issue compilation commands with verbose mode]
endif

What I'd like to achieve is close to the preprocessor in C:

if defined(VERBOSE) || defined(V)
[issue compilation commands with verbose mode]
endif

Do you know how to do that?

ifeq http://stackoverflow.com/questions/7656425/makefile-ifeq-logical-or — Ciro Santilli OurBigBook.com, Jun 24 '16 at 16:56

score 15 · Accepted Answer · answered Nov 16 '12 at 04:54

15

I do like this:

ifneq "$(or $(LINUX_TARGET),$(OSX_TARGET))" ""

endif

Similar to the $(strip approach, but using the more intuitive $(or keyword

answered Nov 16 '12 at 04:54

Jerome

226
2
4

1

Niiiiice, this one's way clearer. I didn't know about the `or`. – Gui13 Dec 16 '12 at 10:29
I switched to accept your answer, because it is semantically exactly solving my issue. – Gui13 Dec 23 '16 at 11:41

score 7 · Answer 2 · answered May 28 '14 at 09:11

7

VERBOSE := $(or $(VERBOSE),$(V))

...then...

ifeq ($(VERBOSE),1)
#Conditional stuff
endif

answered May 28 '14 at 09:11

Rich

71
1
1

score 4 · Answer 3 · 2011-05-16T15:47:16.553

4

As far as I know, the conditional stuff in GNU make doesn't allow for ORs and ANDS. You could always do something like:

ifdef VERBOSE
DOVERBOSE = yes
endif
ifdef V
DOVERBOSE = yes
endif

ifeq( $DOVERBOSE, yes )
    main verbose stuff here
endif

but I don't see why you need to introduce the (hardly self documenting) define of V in the first place.

edited May 16 '11 at 15:47

answered May 16 '11 at 09:30

1

How about `ifdef V \ VERBOSE=v \ endif` and leave the rest as it is? – Beta May 16 '11 at 15:13
@Beta not bad as well! But I like your answer better. – Gui13 May 17 '11 at 07:20

score 4 · Answer 4 · answered May 16 '11 at 15:19

4

I like Neil Butterworth's approach, but if you really want to do it in the style you describe, this will give you OR:

ifneq "$(strip $(VERBOSE) $(V))" ""
[be verbose]
endif

answered May 16 '11 at 15:19

Beta

96,650
16
149
150

score 0 · Answer 5 · answered Oct 28 '15 at 18:08

0

Ok, really late to the party, but I came across this, and wanted to add another solution for others who were looking how to add logic to makefiles: basically, do the logic in a shell, and get the output that way.

ifneq ( $(shell ( [ $(VERBOSE) ] || [ $(V) ] ) && echo y ),)

it seems more convoluted, but if you have an if statement with many ands and ors, this offers a lot of flexibility, and would be easier to read than nested $(and .. $(or ...)) statements.

answered Oct 28 '15 at 18:08

John

3,400
3
31
47

It does "offer a lot of flexibility"--except that it limits you to using the specific shell that you code it to (in your case, BASH) – villapx Apr 25 '16 at 15:47

Conditional OR in makefile

5 Answers5