Problems assigning to LEDs in a case block

Question

When I enter something like this:

always @* begin
    case(SW[17])
        1'b0: assign LEDG = SW[7:0];
        1'b1: assign LEDG = SW[15:8];
    endcase
end

where LEDG is set of [7:0] green LEDs, I get the error:

Error (10137): Verilog HDL Procedural Assignment error at part2.v(20): object "LEDG" on left-hand side of assignment must have a variable data type

upon trying to compile. However, when I put a similar assignment statement outside the case block, such as:

assign LEDG = SW[7:0];

it assigns just fine. I can't seem to figure out the issue.

score 1 · Answer 1 · answered Jan 19 '15 at 17:48

My guess is you have declared LEDG as

wire [7:0] LEDG;

Change it to

reg [7:0] rLEDG;
wire [7:0] LEDG;
assign LEDG = rLEDG;

Your always block should now assign rLEDG.

Basically, always blocks cannot assign to wires, only regs. assign statements on the other hand, assign to wires not regs.

score 0 · Answer 2 · answered Jan 19 '15 at 06:22

0

Assign statements can't be used inside an always block. Remove 'assign' from the line and change your 'output [7:0] LEDG' array to 'output reg [7:0] LEDG' . A reg data type must be used inside always blocks.

answered Jan 19 '15 at 06:22

DJZygote

1
3

score 0 · Answer 3 · edited May 23 '17 at 12:17

Using an assign like that you are most likely not doing what you expect. See using-a-continous-assignment-in-a-verilog-procedure for an explanation of what your currently doing.

To expand in DJZygotes answer, LEDG must be a wire for continuous assign or reg for assignment in an always or initial block.

wire [7:0] LEDG;
assign LEDG = SW[7:0];

Or:

reg [7:0] LEDG;
always @* begin
  case(SW[17])
    1'b0: LEDG = SW[7:0];
    1'b1: LEDG = SW[15:8];
  endcase
end

Problems assigning to LEDs in a case block

3 Answers3