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I'm totally puzzled.

I thought that the following instructions are totally the same:

strb    w0,[x2,w3,uxtw 0] 
strb    w0,[x2,w3,uxtw]

but when I assemble them, I get different encoding:

40 48 23 38     strb w0, [x2, w3, uxtw]
40 58 23 38     strb w0, [x2, w3, uxtw #0]

Any ideas why that's happening?

raff
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    Perhaps related: [What do the \`uxtx\` and \`sxtx\` extensions mean for 32-bit AArch64 \`adds\` instruction?](https://stackoverflow.com/q/72041372) mentions a different redundancy in addressing-mode encoding, between `ldr x0, [x1, x2, sxtx]` and `ldr x0, [x1, x2]` (implicitly `uxtw`, but both are "extending" from 64-bit to 64-bit.) I'd assume your case is another case of redundant ways to encode the same thing when the shift count is zero. – Peter Cordes Apr 21 '23 at 06:31

1 Answers1

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They are syntactically different, but semantically equivalent.

Long story short: it's the shift bit.
The two instructions you show differ in bit 12 (dubbed S in the manual), which determines whether the index register is to be shifted or not. This works the same for all strb, strh and str instructions. The index is always shifted to match the size of the stored operand, so in the case of str xN it's 3, in str wN it's 2, in strh it's 1, and in strb, well, it ends up being 0.

Thus you get this line in the manual, on strb:

<amount>    Is the index shift amount, it must be #0, encoded in "S"
            as 0 if omitted, or as 1 if present.

So one of your instructions doesn't shift the index, the other one shifts it by zero. Great success.

Siguza
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